Present disclosure relates to a method of manufacturing a semiconductor device such as an integrated circuit and transistors and transistor components for an integrated circuit. In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film-forming depositions, etch mask creation, patterning, material etching and removal, as well as doping treatments, are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring/metallization formed above, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor devices in which transistors are stacked on top of each other.
Techniques disclosed in the present disclosure facilitate manufacturing of 3D semiconductor circuits by providing self-alignment techniques for creating multi-tiered (stair-cased) source/drain contacts in three-dimensional logic devices.
It should be noted that an order of different manufacturing steps as described herein is presented for clarity sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of the present disclosure, it is intended that each of the concepts can be executed independently from each other or in combination with each other. Accordingly, the present disclosure can be embodied and viewed in many different ways.
It should be understood that the summary section does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention. Instead, the summary only provides a preliminary discussion of different embodiments and corresponding points of novelty over conventional techniques. Additional details and/or possible perspectives of the disclosure and embodiments should be directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.